Sciweavers

ASYNC
2002
IEEE
161views Hardware» more  ASYNC 2002»
13 years 9 months ago
High-Speed QDI Asynchronous Pipelines
This paper introduces two new high-speed quasi delay insensitive (QDI) asynchronous pipeline templates. These new high throughput templates support complex non-linear pipeline str...
Recep O. Ozdag, Peter A. Beerel
ASYNC
2002
IEEE
123views Hardware» more  ASYNC 2002»
13 years 9 months ago
Improving Smart Card Security Using Self-Timed Circuits
We demonstrate how 1-of-n encoded speed-independent circuits provide a good framework for constructing smart card functions that are resistant to side channel attacks and fault in...
Simon W. Moore, Robert D. Mullins, Paul A. Cunning...
ASYNC
2002
IEEE
115views Hardware» more  ASYNC 2002»
13 years 9 months ago
Point to Point GALS Interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
George S. Taylor, Simon W. Moore, Robert D. Mullin...
ASYNC
2002
IEEE
114views Hardware» more  ASYNC 2002»
13 years 9 months ago
Checking Delay-Insensitivity: 104 Gates and Beyond
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...
Alex Kondratyev, Oriol Roig, Lawrence Neukom, Karl...
ASYNC
2002
IEEE
150views Hardware» more  ASYNC 2002»
13 years 9 months ago
Clock Synchronization through Handshake Signalling
We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems. In contrast to most conventional GALS schemes the method is not...
Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters,...
ASYNC
2002
IEEE
124views Hardware» more  ASYNC 2002»
13 years 9 months ago
Synchronous Interlocked Pipelines
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...
Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Pe...
ASYNC
2002
IEEE
120views Hardware» more  ASYNC 2002»
13 years 9 months ago
Relative Timing Based Verification of Timed Circuits and Systems
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
Peter A. Beerel, Ken S. Stevens, Hoshik Kim
ASYNC
2002
IEEE
90views Hardware» more  ASYNC 2002»
13 years 9 months ago
An Event Spacing Experiment
Events in self-timed rings can propagate evenly spaced or as bursts. By studying these phenomena, we obtain a better understanding of the underlying dynamics of self-timed pipelin...
Mark R. Greenstreet, Anthony Winstanley, Aurelien ...
ASYNC
2002
IEEE
112views Hardware» more  ASYNC 2002»
13 years 9 months ago
A Negative-Overhead, Self-Timed Pipeline
This paper presents a novel variation of wave pipelining that we call “surfing.” In previous wave pipelined designs, timing uncertainty grows monotonically as events propagat...
Mark R. Greenstreet, Brian D. Winters
ASYNC
2002
IEEE
113views Hardware» more  ASYNC 2002»
13 years 9 months ago
A Dual-Mode Synchronous/Asynchronous CORDIC Processor
For application in a software defined radio a CORDIC processor has been developed that can operate both in synchronous and asynchronous mode. Each mode of operation has advantages...
Eckhard Grass, Bodhisatya Sarker, Koushik Maharatn...