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CORR
2006
Springer
90views Education» more  CORR 2006»
9 years 5 months ago
Relatively inertial delays
The paper studies the relatively inertial delays that represent one of the most important concepts in the modeling of the asynchronous circuits.
Serban E. Vlad
CORR
2008
Springer
95views Education» more  CORR 2008»
9 years 5 months ago
Some properties of the regular asynchronous systems
: The asynchronous systems are the models of the asynchronous circuits from the digital electrical engineering. An asynchronous system f is a multi-valued function that assigns to ...
Serban E. Vlad
DAC
2005
ACM
9 years 7 months ago
Asynchronous circuits transient faults sensitivity evaluation
1 This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture, asynchronous circui...
Yannick Monnet, Marc Renaudin, Régis Leveug...
ASPDAC
2001
ACM
127views Hardware» more  ASPDAC 2001»
9 years 9 months ago
High-level design for asynchronous logic
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
Ross Smith, Michiel M. Ligthart
ACSD
2001
IEEE
121views Hardware» more  ACSD 2001»
9 years 9 months ago
A structural encoding technique for the synthesis of asynchronous circuits
This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such ...
Josep Carmona, Jordi Cortadella, Enric Pastor
FORMATS
2006
Springer
9 years 9 months ago
Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of so...
Remy Chevallier, Emmanuelle Encrenaz-Tiphèn...
CHES
2006
Springer
146views Cryptology» more  CHES 2006»
9 years 9 months ago
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...
G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
ASYNC
2004
IEEE
90views Hardware» more  ASYNC 2004»
9 years 9 months ago
Handshake Protocols for De-Synchronization
De-synchronization appears as a new paradigm to automate the design of asynchronous circuits from synchronous netlists. This paper studies different protocols for de-synchronizatio...
Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Lu...
ACSD
2006
IEEE
89views Hardware» more  ACSD 2006»
9 years 9 months ago
On process-algebraic verification of asynchronous circuits
Asynchronous circuits have received much attention recently due to their potential for energy savings. Process algebras have been extensively used in the modelling, analysis and sy...
Xu Wang, Marta Z. Kwiatkowska
ASYNC
1997
IEEE
123views Hardware» more  ASYNC 1997»
9 years 9 months ago
On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic
The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described in this paper. The main advantage of temary logic is the easy realisation of...
Riccardo Mariani, Roberto Roncella, Roberto Salett...
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