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ATS
1998
IEEE
113views Hardware» more  ATS 1998»
9 years 8 months ago
Testing and Diagnosis of Interconnect Structures in FPGAs
Since Field programmable gate arrays (FPGAs) are reprogrammable, faults in them can be easily toleruted once fault sites are located. Previous researches on diagnosis of FPGAs mai...
Sying-Jyan Wang, Chao-Neng Huang
ATS
1998
IEEE
112views Hardware» more  ATS 1998»
9 years 8 months ago
Integrated Current Sensing Device for Micro IDDQ Test
A current sensing device, namely Hall Effect MOSFET (HEMOS) is proposed. It is experimentally shown that the HEMOS enables a non-contacting, and non-disturbing current measurement...
Koichi Nose, Takayasu Sakurai
ATS
1998
IEEE
91views Hardware» more  ATS 1998»
9 years 8 months ago
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunder...
ATS
1998
IEEE
76views Hardware» more  ATS 1998»
9 years 8 months ago
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
Michael S. Hsiao, Srimat T. Chakradhar
ATS
1998
IEEE
114views Hardware» more  ATS 1998»
9 years 8 months ago
Design and Simulation of a RISC-Based 32-bit Embedded On-Board Computer
This paper presents the design and simulation method for developing a RISC-based 32-bit embedded on-board computer. Instead of the conventional breadboarded prototype, (1) we used...
Zhen Guo, He Li, Shuling Guo, Dongsheng Wang
ATS
1998
IEEE
84views Hardware» more  ATS 1998»
9 years 8 months ago
A BIST Structure to Test Delay Faults in a Scan Environment
Patrick Girard, Christian Landrault, V. Moreda, Se...
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
9 years 8 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
ATS
1998
IEEE
106views Hardware» more  ATS 1998»
9 years 8 months ago
A Test Pattern Generation Algorithm Exploiting Behavioral Information
This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level The main problem of using behavioral information for ATPG is the mismatch of timing models bet...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
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