Sciweavers

ATS
2005
IEEE
139views Hardware» more  ATS 2005»
13 years 10 months ago
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability
— Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confid...
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
ATS
2005
IEEE
118views Hardware» more  ATS 2005»
13 years 10 months ago
Partial Gating Optimization for Power Reduction During Test Application
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to...
Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ra...
ATS
2005
IEEE
80views Hardware» more  ATS 2005»
13 years 10 months ago
A Class of Linear Space Compactors for Enhanced Diagnostic
Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja
ATS
2005
IEEE
121views Hardware» more  ATS 2005»
13 years 10 months ago
Compressing Functional Tests for Microprocessors
In the past, test data volume reduction techniques have concentrated heavily on scan test data content. However, functional vectors continue to be utilized because they target uni...
Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas ...
ATS
2005
IEEE
56views Hardware» more  ATS 2005»
13 years 10 months ago
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach
Abstract: Fabrication process improvements and technology scaling results in modifications in the characteristics and in the behavior of manufactured memory chips, which also modi...
Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath
ATS
2005
IEEE
132views Hardware» more  ATS 2005»
13 years 10 months ago
Concurrent Test Generation
We define a new type of test, called “concurrent test,” for a combinational circuit. Given a set of target faults, a concurrent-test is an input vector that detects all (or m...
Vishwani D. Agrawal, Alok S. Doshi