ATVA
2004
Springer
13 years 8 months ago
2004
Springer
ATVA
2004
Springer
13 years 8 months ago
2004
Springer
In this paper, we describe a first-order linear time temporal logic (LTL) model checker based on multiway decision graphs (MDG). We developed a first-order temporal language, LMDG ...
ATVA
2004
Springer
13 years 8 months ago
2004
Springer
While model checking suffers from the state space explosion problem, theorem proving is quite tedious and impractical for verifying complex designs. In this work, we present a veri...
ATVA
2004
Springer
13 years 9 months ago
2004
Springer
ATVA
2004
Springer
13 years 9 months ago
2004
Springer
ATVA
2004
Springer
13 years 9 months ago
2004
Springer
ATVA
2004
Springer
13 years 9 months ago
2004
Springer
Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata Akio Nakata, Tadaaki Tanimoto, Suguru Sasaki, Teruo Higashino Department of Information Networking, ...
ATVA
2004
Springer
13 years 9 months ago
2004
Springer
Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Te...
ATVA
2004
Springer
13 years 9 months ago
2004
Springer
We propose a novel approach to locate errors in complex counterexample of safety property. Our approach measures the distance between two state transition traces with difference o...
ATVA
2004
Springer
13 years 9 months ago
2004
Springer
nded Abstract – Oleg Parshin∗ Abdur Rakib† Stephan Thesing∗ Reinhard Wilhelm∗ The precise determination of worst-case execution times (WCETs) for programs is mostly bein...