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DAC
2012
ACM
8 years 3 months ago
Equivalence checking for behaviorally synthesized pipelines
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
Kecheng Hao, Sandip Ray, Fei Xie
DAC
2012
ACM
8 years 3 months ago
A metric for layout-friendly microarchitecture optimization in high-level synthesis
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
Jason Cong, Bin Liu
ISPD
2012
ACM
252views Hardware» more  ISPD 2012»
8 years 9 months ago
Towards layout-friendly high-level synthesis
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
Jason Cong, Bin Liu 0006, Guojie Luo, Raghu Prabha...
SFM
2011
Springer
253views Formal Methods» more  SFM 2011»
9 years 4 months ago
Application-Layer Connector Synthesis
The heterogeneity characterizing the systems populating the Ubiquitous Computing environment prevents their seamless interoperability. Heterogeneous protocols may be willing to coo...
Paola Inverardi, Romina Spalazzese, Massimo Tivoli
GPEM
2000
126views more  GPEM 2000»
10 years 1 months ago
Automatic Creation of Human-Competitive Programs and Controllers by Means of Genetic Programming
Genetic programming is an automatic method for creating a computer program or other complex structure to solve a problem. This paper first reviews various instances where genetic p...
John R. Koza, Martin A. Keane, Jessen Yu, Forrest ...
ENTCS
2007
130views more  ENTCS 2007»
10 years 1 months ago
Specify, Compile, Run: Hardware from PSL
We propose to use a formal specification language as a high-level hardware description language. Formal languages allow for compact, unambiguous representations and yield designs...
Roderick Bloem, Stefan Galler, Barbara Jobstmann, ...
EURODAC
1995
IEEE
159views VHDL» more  EURODAC 1995»
10 years 5 months ago
The VHDL based design of the MIDA MPEG1 audio decoder
This paper describes the features and design methodology of MIDA, a MPEG1 integrated audio decoder. MIDA has been almost completely designed using automatic synthesis of VHDL desc...
Andrea Finotello, Maurizio Paolini
DATE
2004
IEEE
152views Hardware» more  DATE 2004»
10 years 5 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
ICSE
2010
IEEE-ACM
10 years 6 months ago
Oracle-guided component-based program synthesis
We present a novel approach to automatic synthesis of loopfree programs. The approach is based on a combination of oracle-guided learning from examples, and constraint-based synth...
Susmit Jha, Sumit Gulwani, Sanjit A. Seshia, Ashis...
ISCAS
2002
IEEE
113views Hardware» more  ISCAS 2002»
10 years 6 months ago
Cell library for automatic synthesis of analog error control decoders
This paper presents a cell library for automatic synthesis of analog error control decoders. By using some basic cells, analog error control decoders can be automatically synthesi...
Jie Dai, Chris Winstead, Chris J. Myers, Reid R. H...
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