DAC
2012
ACM
11 years 7 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
DAC
2012
ACM
11 years 7 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
ISPD
2012
ACM
12 years 2 days ago
2012
ACM
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
SFM
2011
Springer
12 years 7 months ago
2011
Springer
The heterogeneity characterizing the systems populating the Ubiquitous Computing environment prevents their seamless interoperability. Heterogeneous protocols may be willing to coo...
GPEM
2000
13 years 4 months ago
2000
Genetic programming is an automatic method for creating a computer program or other complex structure to solve a problem. This paper first reviews various instances where genetic p...
ENTCS
2007
13 years 4 months ago
2007
We propose to use a formal specification language as a high-level hardware description language. Formal languages allow for compact, unambiguous representations and yield designs...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper describes the features and design methodology of MIDA, a MPEG1 integrated audio decoder. MIDA has been almost completely designed using automatic synthesis of VHDL desc...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
ICSE
2010
IEEE-ACM
13 years 9 months ago
2010
IEEE-ACM
We present a novel approach to automatic synthesis of loopfree programs. The approach is based on a combination of oracle-guided learning from examples, and constraint-based synth...
ISCAS
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper presents a cell library for automatic synthesis of analog error control decoders. By using some basic cells, analog error control decoders can be automatically synthesi...