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CSREAESA
2010
10 years 19 days ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton
TVLSI
2002
111views more  TVLSI 2002»
10 years 2 months ago
Circular BIST with state skipping
Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simp...
Nur A. Touba
INTEGRATION
1998
96views more  INTEGRATION 1998»
10 years 2 months ago
BIST for systems-on-a-chip
An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-provide...
Hans-Joachim Wunderlich
JSA
2000
103views more  JSA 2000»
10 years 2 months ago
Testing and built-in self-test - A survey
As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This Built-in Self-Test (BIST) approach not only offers economic benef...
Andreas Steininger
ET
2007
84views more  ET 2007»
10 years 2 months ago
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics
We propose a built-in self-test (BIST) procedure for nanofabrics implemented using chemically assembled electronic nanotechnology. Several fault detection configurations are prese...
Zhanglei Wang, Krishnendu Chakrabarty
ASPDAC
2001
ACM
104views Hardware» more  ASPDAC 2001»
10 years 6 months ago
Processor-programmable memory BIST for bus-connected embedded memories
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...
Ching-Hong Tsai, Cheng-Wen Wu
ICCAD
1997
IEEE
106views Hardware» more  ICCAD 1997»
10 years 6 months ago
BIST TPG for faults in system backplanes
A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems ...
Chen-Huan Chiang, Sandeep K. Gupta
VTS
1998
IEEE
97views Hardware» more  VTS 1998»
10 years 6 months ago
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Mat...
DATE
1998
IEEE
110views Hardware» more  DATE 1998»
10 years 6 months ago
Scheduling and Module Assignment for Reducing Bist Resources
Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resourc...
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breue...
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
10 years 7 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
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