CSREAESA
2010
13 years 2 months ago
2010
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
TVLSI
2002
13 years 4 months ago
2002
Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simp...
INTEGRATION
1998
13 years 4 months ago
1998
An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-provide...
JSA
2000
13 years 4 months ago
2000
As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This Built-in Self-Test (BIST) approach not only offers economic benef...
ET
2007
13 years 4 months ago
2007
We propose a built-in self-test (BIST) procedure for nanofabrics implemented using chemically assembled electronic nanotechnology. Several fault detection configurations are prese...
ASPDAC
2001
ACM
13 years 8 months ago
2001
ACM
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems ...
VTS
1998
IEEE
13 years 8 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resourc...
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...