Sciweavers

TPDS
1998
64views more  TPDS 1998»
13 years 3 months ago
Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors
—Instruction fetching is critical to the performance of a superscalar microprocessor. We develop a mathematical model for three different cache techniques and evaluate its perfor...
Steven Wallace, Nader Bagherzadeh
ISCAPDCS
2001
13 years 5 months ago
A Multiple Blocks Fetch Engine for High Performance Superscalar Processors
The implementation of modern high performance computer is increasingly directed toward parallelism in the hardware. However, most of the current fetch units are limited to one bra...
Yung-Chung Wu, Jong-Jiann Shieh
MICRO
2000
IEEE
71views Hardware» more  MICRO 2000»
13 years 8 months ago
Improving BTB performance in the presence of DLLs
Dynamically Linked Libraries (DLLs) promote software modularity, portability, and flexibility and their use has become widespread. In this paper, we characterize the behavior of f...
Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tys...
SAC
2006
ACM
13 years 10 months ago
Branchless cycle prediction for embedded processors
Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branc...
Kaveh Jokar Deris, Amirali Baniasadi