Sciweavers

TVLSI
1998
80views more  TVLSI 1998»
13 years 9 months ago
Power optimization of core-based systems by address bus encoding
— This paper presents a solution to the problem of reducing the power dissipated by a digital system containing an intellectual proprietary core processor which repeatedly execut...
Luca Benini, Giovanni De Micheli, Enrico Macii, Ma...
IMECS
2007
13 years 10 months ago
Low Power Bus Encoding Technique Considering Coupling Effects
— In this paper, we propose a bus encoding scheme to minimize coupling effects which cause significant power consumption in the on-chip interconnects. The proposed bus encoding s...
H. W. Lin, K. C. Wei
ICCAD
2000
IEEE
148views Hardware» more  ICCAD 2000»
14 years 1 months ago
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed t...
Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, ...
DAC
2004
ACM
14 years 10 months ago
Leakage-and crosstalk-aware bus encoding for total power reduction
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...