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MICRO
2010
IEEE
238views Hardware» more  MICRO 2010»
10 years 11 months ago
Sampling Dead Block Prediction for Last-Level Caches
Last-level caches (LLCs) are large structures with significant power requirements. They can be quite inefficient. On average, a cache block in a 2MB LRU-managed LLC is dead 86% of ...
Samira Manabi Khan, Yingying Tian, Daniel A. Jimen...
CODES
2003
IEEE
11 years 6 months ago
Accurate estimation of cache-related preemption delay
Multitasked real-time systems often employ caches to boost performance. However the unpredictable dynamic behavior of caches makes schedulability analysis of such systems diļ¬ƒcul...
Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudh...
HPCA
2006
IEEE
11 years 7 months ago
Increasing the cache efficiency by eliminating noise
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
Prateek Pujara, Aneesh Aggarwal
ICPP
2007
IEEE
11 years 7 months ago
Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors
Ever-increasing memory footprint of applications and increasing mainstream popularity of shared memory parallel computing motivate us to explore memory compression potential in di...
Lakshmana Rao Vittanala, Mainak Chaudhuri
ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
11 years 10 months ago
Restrictive Compression Techniques to Increase Level 1 Cache Capacity
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access l...
Prateek Pujara, Aneesh Aggarwal
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