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HPDC
2010
IEEE
13 years 5 months ago
New caching techniques for web search engines
This paper proposes a cache hierarchy that enables Web search engines to efficiently process user queries. The different caches in the hierarchy are used to store pieces of data w...
Mauricio Marín, Veronica Gil Costa, Carlos ...
ISCAPDCS
2004
13 years 5 months ago
One-Level Cache Memory Design for Scalable SMT Architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
Muhamed F. Mudawar, John R. Wani
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
13 years 8 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...
ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
13 years 8 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
ICMCS
1999
IEEE
145views Multimedia» more  ICMCS 1999»
13 years 8 months ago
A Bandwidth Friendly Search Engine
The Internet plays host to many millions of documents and images and is increasing in size all the time. As a result locating web content is becoming increasingly difficult for us...
Clare Bradford, Ian W. Marshall
WMPI
2004
ACM
13 years 10 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
13 years 10 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
RTSS
2008
IEEE
13 years 11 months ago
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
Damien Hardy, Isabelle Puaut