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PLDI
1995
ACM
10 years 2 months ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers
ISCA
1994
IEEE
88views Hardware» more  ISCA 1994»
10 years 2 months ago
A Unified Architectural Tradeoff Methodology
Wepresentaunijiedapp?'each to assess thet7adeoff of architecture techniques that affect mean memory access time. The architectural features we consider inciude cache hit Tati...
Chung-Ho Chen, Arun K. Somani
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