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PLDI
1995
ACM
9 years 6 months ago
Tile Size Selection Using Cache Organization and Data Layout
When dense matrix computations are too large to fit in cache, previous research proposes tiling to reduce or eliminate capacity misses. This paper presents a new algorithm for ch...
Stephanie Coleman, Kathryn S. McKinley
ICS
1999
Tsinghua U.
9 years 6 months ago
Adapting cache line size to application behavior
A cache line size has a signi cant e ect on missrate and memorytra c. Today's computers use a xed line size, typically 32B, which may not be optimalfor a given application. O...
Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gup...
SIGMETRICS
2003
ACM
147views Hardware» more  SIGMETRICS 2003»
9 years 7 months ago
Effect of node size on the performance of cache-conscious B+-trees
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
Richard A. Hankins, Jignesh M. Patel
DAC
1999
ACM
10 years 3 months ago
Memory Exploration for Low Power, Embedded Systems
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
Wen-Tsong Shiue, Chaitali Chakrabarti
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