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IESS
2009
Springer
182views Hardware» more  IESS 2009»
13 years 1 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer
SODA
2000
ACM
95views Algorithms» more  SODA 2000»
13 years 5 months ago
Towards a theory of cache-efficient algorithms
We present a model that enables us to analyze the running time of an algorithm on a computer with a memory hierarchy with limited associativity, in terms of various cache parameter...
Sandeep Sen, Siddhartha Chatterjee
ISMVL
2005
IEEE
107views Hardware» more  ISMVL 2005»
13 years 9 months ago
Multiple-Valued Caches for Power-Efficient Embedded Systems
In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded syste...
Emre Özer, Resit Sendag, David Gregg