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CN
1998
64views more  CN 1998»
8 years 9 months ago
Linking Cache Performance to User Behaviour
The performance of HTTP cache servers varies dramatically from server to server. Much of the variation is independent of cache size and network topology and thus appears to be rel...
Ian W. Marshall, Chris M. Roadknight
WSC
2004
8 years 10 months ago
Towards Adaptive Caching for Parallel and Discrete Event Simulation
We investigate factors that impact the effectiveness of caching to speed up discrete event simulation. Walsh and Sirer have shown that a variant of function caching (staged simula...
Abhishek Chugh, Maria Hybinette
CSREAESA
2007
8 years 10 months ago
The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems
- Several studies have shown that cache memories account for more than 40% of the total energy consumed in processor-based embedded systems. In microscale technology nodes, active ...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
CASES
2009
ACM
9 years 16 days ago
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
9 years 1 months ago
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
Jörg Henkel, Tony Givargis, Frank Vahid
ICS
2001
Tsinghua U.
9 years 1 months ago
Analytical cache models with applications to cache partitioning
An accurate, tractable, analytic cache model for time-shared systems is presented, which estimates the overall cache missrate of a multiprocessing system with any cache size and t...
G. Edward Suh, Srinivas Devadas, Larry Rudolph
SPAA
2004
ACM
9 years 2 months ago
Effectively sharing a cache among threads
We compare the number of cache misses M1 for running a computation on a single processor with cache size C1 to the total number of misses Mp for the same computation when using p ...
Guy E. Blelloch, Phillip B. Gibbons
CASES
2004
ACM
9 years 2 months ago
Procedure placement using temporal-ordering information: dealing with code size expansion
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
Christophe Guillon, Fabrice Rastello, Thierry Bida...
GLVLSI
2007
IEEE
172views VLSI» more  GLVLSI 2007»
9 years 3 months ago
The effect of temperature on cache size tuning for low energy embedded systems
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in t...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
HPCA
2002
IEEE
9 years 9 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
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