Sciweavers

ICS
2005
Tsinghua U.
13 years 10 months ago
Reducing latencies of pipelined cache accesses through set prediction
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
Aneesh Aggarwal
ICCS
2005
Springer
13 years 10 months ago
Collecting and Exploiting Cache-Reuse Metrics
Abstract. The increasing gap of processor and main memory performance underlines the need for cache-optimizations, especially on memoryintensive applications. Tools which are able ...
Josef Weidendorfer, Carsten Trinitis
HIPEAC
2005
Springer
13 years 10 months ago
Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation
Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. In this paper, we examine a new multila...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
GCC
2005
Springer
13 years 10 months ago
Coordinated Placement and Replacement for Grid-Based Hierarchical Web Caches
Web caching has been well accepted as a viable method for saving network bandwidth and reducing user access latency. To provide cache sharing on a large scale, hierarchical web cac...
Wenzhong Li, Kun Wu, Xu Ping, Ye Tao, Sanglu Lu, D...
ESA
2005
Springer
161views Algorithms» more  ESA 2005»
13 years 10 months ago
Cache-Oblivious Comparison-Based Algorithms on Multisets
Abstract. We study three comparison-based problems related to multisets in the cache-oblivious model: Duplicate elimination, multisorting and finding the most frequent element (th...
Arash Farzan, Paolo Ferragina, Gianni Franceschini...
ISLPED
2005
ACM
122views Hardware» more  ISLPED 2005»
13 years 10 months ago
A simple mechanism to adapt leakage-control policies to temperature
Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so fa...
Stefanos Kaxiras, Polychronis Xekalakis, Georgios ...
ISLPED
2005
ACM
102views Hardware» more  ISLPED 2005»
13 years 10 months ago
Snug set-associative caches: reducing leakage power while improving performance
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...
Jia-Jhe Li, Yuan-Shin Hwang
ISPASS
2005
IEEE
13 years 10 months ago
Balancing Performance and Reliability in the Memory Hierarchy
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurate...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
ISMVL
2005
IEEE
107views Hardware» more  ISMVL 2005»
13 years 10 months ago
Multiple-Valued Caches for Power-Efficient Embedded Systems
In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded syste...
Emre Özer, Resit Sendag, David Gregg
ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
13 years 10 months ago
The V-Way Cache: Demand Based Associativity via Global Replacement
As processor speeds increase and memory latency becomes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of curr...
Moinuddin K. Qureshi, David Thompson, Yale N. Patt