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ISLPED
2006
ACM
119views Hardware» more  ISLPED 2006»
10 years 8 months ago
Process variation aware cache leakage management
In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a...
Ke Meng, Russ Joseph
ERLANG
2006
ACM
10 years 8 months ago
Concurrent caching
A concurrent cache design is presented which allows cached data to be spread across a cluster of computers. The implementation s persistent storage from cache storage and abstract...
Jay Nelson
CF
2006
ACM
10 years 8 months ago
Improving the memory behavior of vertical filtering in the discrete wavelet transform
The discrete wavelet transform (DWT) is used in several image and video compression standards, in particular JPEG2000. A 2D DWT consists of horizontal filtering along the rows fo...
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamati...
CASES
2006
ACM
10 years 8 months ago
Reducing energy of virtual cache synonym lookup using bloom filters
Virtual caches are employed as L1 caches of both high performance and embedded processors to meet their short latency requirements. However, they also introduce the synonym proble...
Dong Hyuk Woo, Mrinmoy Ghosh, Emre Özer, Stua...
ACMMSP
2006
ACM
247views Hardware» more  ACMMSP 2006»
10 years 8 months ago
A flexible data to L2 cache mapping approach for future multicore processors
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cach...
Lei Jin, Hyunjin Lee, Sangyeun Cho
WISE
2006
Springer
10 years 8 months ago
SCEND: An Efficient Semantic Cache to Adequately Explore Answerability of Views
Maintaining a semantic cache of materialized XPath views inside or outside the database, is a novel, feasible and efficient approach to accelerate XML query processing. However, th...
Guoliang Li, Jianhua Feng, Na Ta, Yong Zhang, Lizh...
RTSS
2006
IEEE
10 years 8 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
RTAS
2006
IEEE
10 years 8 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
MICRO
2006
IEEE
162views Hardware» more  MICRO 2006»
10 years 8 months ago
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...
Ranjith Subramanian, Yannis Smaragdakis, Gabriel H...
MICRO
2006
IEEE
102views Hardware» more  MICRO 2006»
10 years 8 months ago
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multi...
Sangyeun Cho, Lei Jin
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