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CGO
2006
IEEE
10 years 8 months ago
A Cross-Architectural Interface for Code Cache Manipulation
Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentiallyaltered copy of ever...
Kim M. Hazelwood, Robert S. Cohn
HIPEAC
2007
Springer
10 years 8 months ago
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
Sonia López, Steve Dropsho, David H. Albone...
HIPC
2007
Springer
10 years 8 months ago
Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors
Traditional directory-based cache coherence protocols suffer from long-latency cache misses as a consequence of the indirection introduced by the home node, which must be accessed...
Alberto Ros, Manuel E. Acacio, José M. Garc...
FPL
2007
Springer
141views Hardware» more  FPL 2007»
10 years 8 months ago
Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration
The effect of kernel operations on cache optimisations in a soft-core reconfigurable system is important for dynamic cache switching design. Considering kernel operations changes ...
John Shield, Peter Sutton, Philip Machanick
NOCS
2007
IEEE
10 years 9 months ago
The Power of Priority: NoC Based Distributed Cache Coherency
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...
NAS
2007
IEEE
10 years 9 months ago
An Efficient SAN-Level Caching Method Based on Chunk-Aging
: SAN-level caching can manage caching within a global view so that global hot data can be identified and cached. However, two problems may be encountered in the existing SAN-level...
Jiwu Shu, Yang Wang 0009, Wei Xue, Yifeng Luo
MSS
2007
IEEE
83views Hardware» more  MSS 2007»
10 years 9 months ago
The RAM Enhanced Disk Cache Project (REDCAP)
This paper presents the RAM Enhanced Disk Cache Project, REDCAP, a new cache of disk blocks which reduces the read I/O time by using a small portion of the main memory. The essent...
Pilar Gonzalez-Ferez, Juan Piernas, Toni Cortes
MICRO
2007
IEEE
120views Hardware» more  MICRO 2007»
10 years 9 months ago
Scavenger: A New Last Level Cache Architecture with Global Block Priority
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of inte...
Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Maina...
ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
10 years 9 months ago
Performance of Graceful Degradation for Cache Faults
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
10 years 9 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
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