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CODES
2007
IEEE
10 years 9 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
RTSS
2008
IEEE
10 years 9 months ago
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
Damien Hardy, Isabelle Puaut
RTCSA
2008
IEEE
10 years 9 months ago
Impact of Cache Partitioning on Multi-tasking Real Time Embedded Systems
Cache partitioning techniques have been proposed in the past as a solution for the cache interference problem. Due to qualitative differences with general purpose platforms, real-...
Bach Duy Bui, Marco Caccamo, Lui Sha, Joseph Marti...
MICRO
2008
IEEE
111views Hardware» more  MICRO 2008»
10 years 9 months ago
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...
Livio Soares, David K. Tam, Michael Stumm
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
10 years 9 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
10 years 9 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
ISVLSI
2008
IEEE
156views VLSI» more  ISVLSI 2008»
10 years 9 months ago
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways
The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistor...
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihar...
IISWC
2008
IEEE
10 years 9 months ago
Evaluating the impact of dynamic binary translation systems on hardware cache performance
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
Arkaitz Ruiz-Alvarez, Kim M. Hazelwood
IEEEPACT
2008
IEEE
10 years 9 months ago
Characterizing and modeling the behavior of context switch misses
One of the essential features in modern computer systems is context switching, which allows multiple threads of execution to time-share a limited number of processors. While very ...
Fang Liu, Fei Guo, Yan Solihin, Seongbeom Kim, Abd...
ICPP
2008
IEEE
10 years 9 months ago
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
Lei Jin, Sangyeun Cho
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