CAL
2006
13 years 4 months ago
2006
This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial ...
CAL
2006
13 years 4 months ago
2006
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
CAL
2006
13 years 4 months ago
2006
Instruction-level traces are widely used for program and hardware analysis. However, program traces for just a few seconds of execution are enormous, up to several terabytes in siz...
CAL
2006
13 years 4 months ago
2006
Abstract-- Transactional memory has great potential for simplifying multithreaded programming by allowing programmers to specify regions of the program that must appear to execute ...
CAL
2006
13 years 4 months ago
2006
Chip multiprocessors are of increasing importance due to recent difficulties in achieving higher clock frequencies in uniprocessors, but their success depends on finding useful wor...
CAL
2006
13 years 4 months ago
2006
User-level communication alleviates the software overhead of the communication subsystem by allowing applications to access the network interface directly. For that purpose, effici...
CAL
2006
13 years 4 months ago
2006
Abstract-- We propose and evaluate User-Driven Frequency Scaling (UDFS) for improved power management on processors that support Dynamic Voltage and Frequency Scaling (DVFS), e.g, ...
CAL
2006
13 years 4 months ago
2006
Modern programming languages often include complex mechanisms for dynamic memory allocation and garbage collection. These features drive the need for more efficient implementation ...
CAL
2006
13 years 4 months ago
2006
Multiple core designs have become commonplace in the processor market, and are hence a major focus in modern computer architecture research. Thus, for both product development and ...
CAL
2006
13 years 4 months ago
2006
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...