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DAC
2005
ACM
11 years 10 months ago
Spatially distributed 3D circuit models
Spatially distributed 3D circuit models are extracted with a segmentto-segment BEM (Boundary Element Method) algorithm for both capacitance and inverse inductance couplings rather...
Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byr...
ASPDAC
2005
ACM
78views Hardware» more  ASPDAC 2005»
11 years 10 months ago
Timing driven track routing considering coupling capacitance
Abstract— As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven ro...
Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra
ASPDAC
2007
ACM
99views Hardware» more  ASPDAC 2007»
12 years 2 days ago
Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion
Youngmin Kim, Dusan Petranovic, Dennis Sylvester
DAC
1999
ACM
12 years 12 days ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
12 years 1 months ago
Interconnect capacitance extraction for system LCD circuits
This paper discusses interconnect capacitance extraction for system LCD circuits, where coupling capacitance is much significant since a ground plane locates far away unlike LSI ...
Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimot...
ISQED
2006
IEEE
89views Hardware» more  ISQED 2006»
12 years 2 months ago
Study of Floating Fill Impact on Interconnect Capacitance
It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating ...
Andrew B. Kahng, Kambiz Samadi, Puneet Sharma
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