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CASES
2008
ACM
13 years 6 months ago
A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount o...
Chengmo Yang, Alex Orailoglu
CASES
2008
ACM
13 years 6 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...
CASES
2008
ACM
13 years 6 months ago
Cache-aware cross-profiling for java processors
Performance evaluation of embedded software is essential in an early development phase so as to ensure that the software will run on the embedded device's limited computing r...
Walter Binder, Alex Villazón, Martin Schoeb...
CASES
2008
ACM
13 years 6 months ago
Active control and digital rights management of integrated circuit IP cores
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
Yousra Alkabani, Farinaz Koushanfar
CASES
2008
ACM
13 years 6 months ago
Execution context optimization for disk energy
Power, energy, and thermal concerns have constrained embedded systems designs. Computing capability and storage density have increased dramatically, enabling the emergence of hand...
Jerry Hom, Ulrich Kremer
CASES
2008
ACM
13 years 6 months ago
Compiling custom instructions onto expression-grained reconfigurable architectures
While customizable processors aim at combining the flexibility of general purpose processors with the speed and power advantages of custom circuits, commercially available process...
Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi
CASES
2008
ACM
13 years 6 months ago
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
Houman Homayoun, Mohammad A. Makhzan, Alexander V....
CASES
2008
ACM
13 years 6 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano