Sciweavers

CASES
2009
ACM
13 years 11 months ago
Hardware evaluation of the Luffa hash family
Efficient hardware architectures for the Luffa hash algorithm are proposed in this work. We explore different tradeoffs and propose several architectures, targeting both compac...
Miroslav Knezevic, Ingrid Verbauwhede
CASES
2009
ACM
13 years 11 months ago
Fine-grain performance scaling of soft vector processors
Embedded systems are often implemented on FPGA devices and 25% of the time [2] include a soft processor— a processor built using the FPGA reprogrammable fabric. Because of their...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
CASES
2009
ACM
13 years 11 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke
CASES
2009
ACM
13 years 11 months ago
Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system
A common problem in event-triggered real-time systems is caused by low-priority tasks that are implemented as interrupt handlers interrupting and disturbing high-priority tasks th...
Fabian Scheler, Wanja Hofer, Benjamin Oechslein, R...
CASES
2009
ACM
13 years 11 months ago
Towards scalable reliability frameworks for error prone CMPs
As technology scales and the energy of computation continually approaches thermal equilibrium [1,2], parameter variations and noise levels will lead to larger error rates at vario...
Joseph Sloan, Rakesh Kumar
CASES
2009
ACM
13 years 11 months ago
An accelerator-based wireless sensor network processor in 130nm CMOS
Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Over the...
Mark Hempstead, Gu-Yeon Wei, David Brooks
CASES
2009
ACM
13 years 11 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
CASES
2009
ACM
13 years 11 months ago
Tight WCRT analysis of synchronous C programs
Accurate estimation of the tick length of a synchronous program is essential for efficient and predictable implementations that are devoid of timing faults. The techniques to dete...
Partha S. Roop, Sidharta Andalam, Reinhard von Han...
CASES
2009
ACM
13 years 11 months ago
Optimal loop parallelization for maximizing iteration-level parallelism
This paper solves the open problem of extracting the maximal number of iterations from a loop that can be executed in parallel on chip multiprocessors. Our algorithm solves it opt...
Duo Liu, Zili Shao, Meng Wang, Minyi Guo, Jingling...
CASES
2009
ACM
13 years 11 months ago
A platform for developing adaptable multicore applications
Computer systems are resource constrained. Application adaptation is a useful way to optimize system resource usage while satisfying the application performance constraints. Previ...
Dan Fay, Li Shang, Dirk Grunwald