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CDES
2006
100views Hardware» more  CDES 2006»
13 years 5 months ago
Towards a Nanoscale Artificial Cortex
Alice C. Parker, Aaron K. Friesz, Afshaneh Pakdama...
CDES
2006
136views Hardware» more  CDES 2006»
13 years 5 months ago
Using Task Recomputation During Application Mapping in Parallel Embedded Architectures
- Many memory-sensitive embedded applications can tolerate small performance degradations if doing so can reduce the memory space requirements significantly. This paper explores th...
Suleyman Tosun, Mahmut T. Kandemir, Hakduran Koc
CDES
2006
78views Hardware» more  CDES 2006»
13 years 5 months ago
The Impact of Cache Organization in Optimizing Microprocessor Power Consumption
In the recent years, power consumption has become increasingly an important design concern as silicon area and performance in modern computer systems design. Several factors have ...
Nagm Mohamed, Nazeih Botros, Wei Zhang
CDES
2006
100views Hardware» more  CDES 2006»
13 years 5 months ago
Integrity and Integration Issues for Nano-Tube Based Interconnect Systems
: As we continue miniaturization of circuits into nano-scale, interconnects have been recognized as the limiting factor for next generation of computing structures. To increase the...
Tulin Mangir
CDES
2006
112views Hardware» more  CDES 2006»
13 years 5 months ago
A New Processor Architecture with a New Program Driving Method
- This paper proposes a new type of processor architecture using a new program driving method which makes it possible for more programs to run in a single kernel processor concurre...
Xiaobo Li, Ke Luo, Xiangdong Cui, Lalin Jiang, Xia...
CDES
2006
87views Hardware» more  CDES 2006»
13 years 5 months ago
A Configuration Concept for a Massively Parallel FPGA Architecture
Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfei...
CDES
2006
84views Hardware» more  CDES 2006»
13 years 5 months ago
Simulation of a Turing Machine using EndoII Splicing Rules
In this paper we define splicing rules for class II restriction endonucleases and show how a Turing Machine can be simulated using such rules.
Kamala Kritihivasan, Anshu Bhatia, T. S. Chandra
CDES
2006
158views Hardware» more  CDES 2006»
13 years 5 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
CDES
2006
80views Hardware» more  CDES 2006»
13 years 5 months ago
Communicating Distributed H systems with Simple Splicing Rules
In this paper we define communicating distributed H systems with simple splicing rules of types (1,3), (1,4) and (2,3) and study the generative capacity. keyword: Splicing systems,...
Kamala Krithivasan, Prahladh Harsha, Muralidhar Ta...
CDES
2006
96views Hardware» more  CDES 2006»
13 years 5 months ago
Semi-Contiguous Memory Allocation for Efficient Sequential-Access
Many algorithms have been devised and studied for dynamic contiguous memory allocation. In the absence of enough contiguous memory to satisfy a particular request, one approach is...
Elias G. Khalaf, Ralph Tucci