CDES
2006
13 years 6 months ago
2006
Abstract--This paper describes an architecture of FPGAlike fabric for future hybrid "CMOL" circuits. Such circuits will combine a semiconductor-transistor (CMOS) stack an...
CDES
2006
13 years 6 months ago
2006
We survey a set of flip-flops designed for low power and high performance. We highlight the basic features of these flip-flops and evaluate them based on timing characteristics, po...
CDES
2006
13 years 6 months ago
2006
CDES
2006
13 years 6 months ago
2006
- Many memory-sensitive embedded applications can tolerate small performance degradations if doing so can reduce the memory space requirements significantly. This paper explores th...
CDES
2006
13 years 6 months ago
2006
In the recent years, power consumption has become increasingly an important design concern as silicon area and performance in modern computer systems design. Several factors have ...
CDES
2006
13 years 6 months ago
2006
: As we continue miniaturization of circuits into nano-scale, interconnects have been recognized as the limiting factor for next generation of computing structures. To increase the...
CDES
2006
13 years 6 months ago
2006
- This paper proposes a new type of processor architecture using a new program driving method which makes it possible for more programs to run in a single kernel processor concurre...
CDES
2006
13 years 6 months ago
2006
CDES
2006
13 years 6 months ago
2006
In this paper we define splicing rules for class II restriction endonucleases and show how a Turing Machine can be simulated using such rules.
CDES
2006
13 years 6 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...