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    DAC
    2006
    ACM
    176views Computer Architecture» more  DAC 2006»
    Statistical logic cell delay analysis using a current-based model
    14 years 5 months ago
    Statistical logic cell delay analysis using a current-based model
    Download  homepages.cae.wisc.edu
    A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
    Hanif Fatemi, Shahin Nazarian, Massoud Pedram
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