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ISPD
2007
ACM
151views Hardware» more  ISPD 2007»
13 years 6 months ago
Pattern sensitive placement for manufacturability
When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge...
Shiyan Hu, Jiang Hu
VLSID
1996
IEEE
119views VLSI» more  VLSID 1996»
13 years 8 months ago
Parallel simulated annealing strategies for VLSI cell placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process, and as a result several research efforts have been un...
John A. Chandy, Prithviraj Banerjee
ISPD
2005
ACM
168views Hardware» more  ISPD 2005»
13 years 10 months ago
Capo: robust and scalable open-source min-cut floorplacer
In this invited note we describe Capo, an open-source software tool for cell placement, mixed-size placement and floorplanning with emphasis on routability. Capo is among the fas...
Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hay...
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
13 years 10 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen