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CHARME
2005
Springer
91views Hardware» more  CHARME 2005»
13 years 10 months ago
Temporal Modalities for Concisely Capturing Timing Diagrams
Timing diagrams are useful for capturing temporal specifications in which all mentioned events are required to occur. We first show that translating timing diagrams with both par...
Hana Chockler, Kathi Fisler
CHARME
2005
Springer
94views Hardware» more  CHARME 2005»
13 years 10 months ago
Verifying Quantitative Properties Using Bound Functions
Abstract. We define and study a quantitative generalization of the traditional boolean framework of model-based specification and verification. In our setting, propositions have...
Arindam Chakrabarti, Krishnendu Chatterjee, Thomas...
CHARME
2005
Springer
106views Hardware» more  CHARME 2005»
13 years 10 months ago
Error Detection Using BMC in a Parallel Environment
In this paper, we explore a parallelization of BMC based on state space partitioning. The parallelization is accomplished by executing multiple instances of BMC independently from ...
Subramanian K. Iyer, Jawahar Jain, Mukul R. Prasad...
CHARME
2005
Springer
122views Hardware» more  CHARME 2005»
13 years 10 months ago
Regular Vacuity
The application of model-checking tools to complex systems involves a nontrivial step of modelling the system by a finite-state model and a translation of the desired properties i...
Doron Bustan, Alon Flaisher, Orna Grumberg, Orna K...
CHARME
2005
Springer
133views Hardware» more  CHARME 2005»
13 years 10 months ago
Symbolic Partial Order Reduction for Rule Based Transition Systems
Partial order (PO) reduction methods are widely employed to combat state explosion during model-checking. In this paper, we develop a partial order reduction algorithm for rule-bas...
Ritwik Bhattacharya, Steven M. German, Ganesh Gopa...
CHARME
2005
Springer
120views Hardware» more  CHARME 2005»
13 years 10 months ago
How Thorough Is Thorough Enough?
Abstraction is the key for effectively dealing with the state explosion in model-checking. Unfortunately, finding abstractions which are small and yet enable us to get conclusive ...
Arie Gurfinkel, Marsha Chechik
CHARME
2005
Springer
136views Hardware» more  CHARME 2005»
13 years 10 months ago
Acceleration of SAT-Based Iterative Property Checking
Today, verification is becoming the dominating factor for successful circuit designs. In this context formal verification techniques allow to prove the correctness of a circuit ...
Daniel Große, Rolf Drechsler
CHARME
2005
Springer
176views Hardware» more  CHARME 2005»
13 years 10 months ago
An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment
Abstract. Model checking is a formal technique for automatically verifying that a finite-state model satisfies a temporal property. In model checking, generally Binary Decision D...
Nina Amla, Xiaoqun Du, Andreas Kuehlmann, Robert P...