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    DFT
    2009
    IEEE
    139views VLSI» more  DFT 2009»
    Reduced Precision Checking for a Floating Point Adder
    13 years 7 months ago
    Reduced Precision Checking for a Floating Point Adder
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    We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. O...
    Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin
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