Sciweavers

ICS
1999
Tsinghua U.
13 years 8 months ago
Improving the performance of speculatively parallel applications on the Hydra CMP
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
Kunle Olukotun, Lance Hammond, Mark Willey
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
13 years 8 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
13 years 9 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
13 years 9 months ago
A methodology for the characterization of process variation in NoC links
—Associated with the ever growing integration scales is the increase in process variability. In the context of networkon-chip, this variability affects the maximum frequency that...
Carles Hernandez, Federico Silla, José Duat...
MICRO
2005
IEEE
136views Hardware» more  MICRO 2005»
13 years 9 months ago
Automatic Thread Extraction with Decoupled Software Pipelining
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I...