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ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
13 years 1 months ago
Improved on-chip router analytical power and area modeling
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
Andrew B. Kahng, Bill Lin, Kambiz Samadi
DM
2002
86views more  DM 2002»
13 years 3 months ago
A chip-firing game and Dirichlet eigenvalues
We consider a variation of the chip-firing game in a induced subgraph S of a graph G. Starting from a given chip configuration, if a vertex v has at least as many chips as its deg...
Fan R. K. Chung, Robert B. Ellis
BMCBI
2005
82views more  BMCBI 2005»
13 years 3 months ago
Quality assessment of microarrays: Visualization of spatial artifacts and quantitation of regional biases
Background: Quality-control is an important issue in the analysis of gene expression microarrays. One type of problem is regional bias, in which one region of a chip shows artifac...
Mark Reimers, John N. Weinstein
SIAMDM
2008
79views more  SIAMDM 2008»
13 years 3 months ago
Reconfigurations in Graphs and Grids
Let G be a connected graph, and let V and V two n-element subsets of its vertex set V (G). Imagine that we place a chip at each element of V and we want to move them into the posi...
Gruia Calinescu, Adrian Dumitrescu, János P...
CAL
2007
13 years 3 months ago
Microarchitectures for Managing Chip Revenues under Process Variations
—As transistor feature sizes continue to shrink into the sub-90nm range and beyond, the effects of process variations on critical path delay and chip yields have amplified. A com...
Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph...
BMCBI
2010
87views more  BMCBI 2010»
13 years 3 months ago
poolMC: Smart pooling of mRNA samples in microarray experiments
Background: Typically, pooling of mRNA samples in microarray experiments implies mixing mRNA from several biological-replicate samples before hybridization onto a microarray chip....
Raghunandan M. Kainkaryam, Angela Bruex, Anna C. G...
SODA
2008
ACM
105views Algorithms» more  SODA 2008»
13 years 5 months ago
Deterministic random walks on regular trees
Jim Propp's rotor router model is a deterministic analogue of a random walk on a graph. Instead of distributing chips randomly, each vertex serves its neighbors in a fixed or...
Joshua N. Cooper, Benjamin Doerr, Tobias Friedrich...
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
13 years 7 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
NANONET
2009
Springer
199views Chemistry» more  NANONET 2009»
13 years 8 months ago
Through Silicon Via-Based Grid for Thermal Control in 3D Chips
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
José L. Ayala, Arvind Sridhar, Vinod Pangra...
DFT
2003
IEEE
86views VLSI» more  DFT 2003»
13 years 9 months ago
CROWNE: Current Ratio Outliers with Neighbor Estimator
Increased leakage and process variations make distinction between fault-free and faulty chips by IDDQ test difficult. Earlier the concept of Current Ratios (CR) was proposed to sc...
Sagar S. Sabade, D. M. H. Walker