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TCAD
2010
154views more  TCAD 2010»
12 years 11 months ago
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style
In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the sa...
Fu-Wei Chen, Yi-Yu Liu
DAC
2005
ACM
13 years 6 months ago
Template-driven parasitic-aware optimization of analog integrated circuit layouts
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J...
ISCAS
2007
IEEE
79views Hardware» more  ISCAS 2007»
13 years 10 months ago
Impact of strain on the design of low-power high-speed circuits
- In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has be...
H. Ramakrishnan, K. Maharatna, S. Chattopadhyay, A...
ICCAD
2007
IEEE
132views Hardware» more  ICCAD 2007»
14 years 1 months ago
Principle Hessian direction based parameter reduction with process variation
— As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a Principle Hessi...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...
DAC
2004
ACM
14 years 5 months ago
Toward a systematic-variation aware timing methodology
Variability of circuit performance is becoming a very important issue for ultra-deep sub-micron technology. Gate length variation has the most direct impact on circuit performance...
Puneet Gupta, Fook-Luen Heng