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TVLSI
2002
79views more  TVLSI 2002»
8 years 11 months ago
Electrical and optical clock distribution networks for gigascale microprocessors
A summary of electrical and optical approaches to clock distribution within high-performance microprocessors is presented. System-level properties of intrachip electrical clock dis...
A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, J...
CSREAESA
2004
9 years 1 months ago
A Distributed FIFO Scheme for System on Chip Inter-Component Communication
Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because the wires do not scale as fast as the device...
Ray Robert Rydberg III, Jabulani Nyathi, Jos&eacut...
ASPDAC
2005
ACM
130views Hardware» more  ASPDAC 2005»
9 years 1 months ago
Stability analysis of active clock deskewing systems using a control theoretic approach
β€” In this paper, a methodology for analyzing closed loop clock distribution and active deskewing networks is proposed. An active clock distribution and deskewing network is model...
Vinil Varghese, Tom Chen, Peter Young
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
9 years 4 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
DAC
1999
ACM
9 years 4 months ago
A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
9 years 5 months ago
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory
β€” A formal methodology for the analysis of a closed loop clock distribution and active deskewing network is proposed. In this paper an active clock distribution and deskewing net...
Vinil Varghese, Tom Chen, Peter Michael Young
DATE
2009
IEEE
102views Hardware» more  DATE 2009»
9 years 6 months ago
Register placement for high-performance circuits
β€”In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthe...
Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura
ICCD
2001
IEEE
90views Hardware» more  ICCD 2001»
9 years 8 months ago
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs
Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked...
Martin Saint-Laurent, Madhavan Swaminathan, James ...
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