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119
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ICCAD
2004
IEEE
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ICCAD 2004
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A yield improvement methodology using pre- and post-silicon statistical clock scheduling
15 years 11 months ago
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vlsi.ece.wisc.edu
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
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