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DAC
2005
ACM
10 years 4 months ago
Minimizing peak current via opposite-phase clock tree
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
10 years 4 months ago
Skew scheduling and clock routing for improved tolerance to process variations
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu
ASPDAC
2008
ACM
169views Hardware» more  ASPDAC 2008»
10 years 5 months ago
Buffered clock tree synthesis for 3D ICs under thermal variations
In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides...
Jacob R. Minz, Xin Zhao, Sung Kyu Lim
ASPDAC
2008
ACM
129views Hardware» more  ASPDAC 2008»
10 years 5 months ago
Clock tree synthesis with data-path sensitivity matching
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
10 years 6 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
DATE
1998
IEEE
76views Hardware» more  DATE 1998»
10 years 7 months ago
Gated Clock Routing Minimizing the Switched Capacitance
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
Jaewon Oh, Massoud Pedram
ISPD
2000
ACM
126views Hardware» more  ISPD 2000»
10 years 7 months ago
A practical clock tree synthesis for semi-synchronous circuits
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...
Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui,...
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
10 years 8 months ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
10 years 8 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
10 years 8 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
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