ISCA
2002
IEEE
13 years 9 months ago
2002
IEEE
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
INFOCOM
2002
IEEE
13 years 9 months ago
2002
IEEE
Abstract—Packet delay traces are important measurements for analyzing end-to-end performance and for designing traffic control algorithms in computer networks. Due to the fact t...
ASYNC
2002
IEEE
13 years 9 months ago
2002
IEEE
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
ASYNC
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems. In contrast to most conventional GALS schemes the method is not...
WSNA
2003
ACM
13 years 9 months ago
2003
ACM
We consider the problem of synchronization of all clocks in a sensor network, in the regime of asymptotically high node densities. We formulate this problem as one in which all cl...
ISLPED
2003
ACM
13 years 9 months ago
2003
ACM
Enabled by the continuous advancement in fabrication technology, present day synchronous microprocessors include more than 100 million transistors and have clock speeds well in ex...
DAC
2003
ACM
13 years 9 months ago
2003
ACM
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
ISVLSI
2003
IEEE
13 years 9 months ago
2003
IEEE
Abstract— Dissipation in the clock tree and state elements of ASIC designs is often a significant fraction of total energy consumption. We propose a methodology for recovering m...
DSN
2003
IEEE
13 years 9 months ago
2003
IEEE
Clock-related operations are one of the many sources of replica non-determinism and of replica inconsistency in fault-tolerant distributed systems. In passive replication, if the ...
DATE
2003
IEEE
13 years 9 months ago
2003
IEEE
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...