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ISQED
2007
IEEE
127views Hardware» more  ISQED 2007»
13 years 10 months ago
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Ch...
ISQED
2007
IEEE
120views Hardware» more  ISQED 2007»
13 years 10 months ago
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, ...
ICC
2007
IEEE
142views Communications» more  ICC 2007»
13 years 10 months ago
Generalized CRLB for DA and NDA Synchronization of UWB Signals with Clock Offset
—In this paper the Cramér-Rao lower bound (CRLB) of an ultra-wideband (UWB) pulse amplitude modulated (PAM) signal with time hopping (TH) code is derived for the practical case ...
Saeed Khalesehosseini, John Nielsen
DATE
2007
IEEE
65views Hardware» more  DATE 2007»
13 years 10 months ago
Clock-frequency assignment for multiple clock domain systems-on-a-chip
Modern systems-on-a-chip platforms support multiple clock domains, in which different sub-circuits are driven by different clock signals. Although the frequency of each domain can...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
ISVLSI
2008
IEEE
125views VLSI» more  ISVLSI 2008»
13 years 10 months ago
Energy Recovery from High-Frequency Clocks Using DC-DC Converters
Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large cap...
Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Sha...
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
13 years 10 months ago
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
ICCD
2008
IEEE
142views Hardware» more  ICCD 2008»
13 years 10 months ago
Gate planning during placement for gated clock network
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
FOCS
2008
IEEE
13 years 10 months ago
Clock Synchronization with Bounded Global and Local Skew
We present a distributed clock synchronization algorithm that guarantees an exponentially improved bound of O(log D) on the clock skew between neighboring nodes in any graph G of ...
Christoph Lenzen, Thomas Locher, Roger Wattenhofer
DATE
2008
IEEE
157views Hardware» more  DATE 2008»
13 years 10 months ago
Clock Distribution Scheme using Coplanar Transmission Lines
The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signali...
Victor H. Cordero, Sunil P. Khatri
ALGOSENSORS
2009
Springer
13 years 11 months ago
Near-Optimal Radio Use for Wireless Network Synchronization
In this paper we consider the model of communication where wireless devices can either switch their radios off to save energy (and hence, can neither send nor receive messages), o...
Milan Bradonjic, Eddie Kohler, Rafail Ostrovsky