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ISCAS
2011
IEEE
217views Hardware» more  ISCAS 2011»
12 years 8 months ago
A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC
— A switched-capacitor single-stage sigma-delta ADC with a fifth-order modulator is proposed. The proposed sigmadelta ADC employs feed-forward architecture with oversampling rati...
Chang-Seob Shin, Min-Ho Yoon, Kang-Il Cho, Young-J...
TVLSI
2008
99views more  TVLSI 2008»
13 years 4 months ago
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
Sheng-Chih Lin, Kaustav Banerjee
PATMOS
2004
Springer
13 years 9 months ago
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
ISCAS
2005
IEEE
144views Hardware» more  ISCAS 2005»
13 years 10 months ago
Cascode buffer for monolithic voltage conversion operating at high input supply voltages
A high-to-low switching DC-DC converter that operates at input supply voltages up to two times as high as the maximum voltage permitted in a nanometer CMOS technology is proposed ...
Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Fr...
VLSID
2005
IEEE
223views VLSI» more  VLSID 2005»
14 years 4 months ago
A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design
A novel topology for Translinear (TL) loops comprising of CMOS Second Generation Current Conveyors (CC-II) and diodes is proposed. The proposed methodology opens a new paradigm to...
Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee...