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ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
10 years 6 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos
ISCAS
2007
IEEE
78views Hardware» more  ISCAS 2007»
10 years 6 months ago
Towards Automated Power Gating of Registers using CoDeL
— In this paper, we use the CoDeL platform to develop test circuits and analyze the potential and performance impact of power gating individual registers. For each register, we e...
Nainesh Agarwal, Nikitas J. Dimopoulos
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