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CODES
2006
IEEE
11 years 1 months ago
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
A key step in the design of multi-rate real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure as caused by bounded buff...
Maarten Wiggers, Marco Bekooij, Pierre G. Jansen, ...
CODES
2006
IEEE
11 years 1 months ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
CODES
2006
IEEE
11 years 3 months ago
Application-specific workload shaping in multimedia-enabled personal mobile devices
Today, most personal mobile devices (e.g. cell phones and PDAs) are multimedia-enabled and support a variety of concurrently running applications such as audio/video players, word...
Balaji Raman, Samarjit Chakraborty
CODES
2006
IEEE
11 years 3 months ago
Phase guided sampling for efficient parallel application simulation
Simulating chip-multiprocessor systems (CMP) can take a long time. For single-threaded workloads, earlier work has shown the utility of phase analysis, that is identification of r...
Jeffrey Namkung, Dohyung Kim, Rajesh K. Gupta, Igo...
CODES
2006
IEEE
11 years 3 months ago
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instructio...
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswar...
CODES
2006
IEEE
11 years 3 months ago
Automatic selection of application-specific instruction-set extensions
In this paper, we present a general and an efficient algorithm for automatic selection of new application-specific instructions under hardware resources constraints. The instructi...
Carlo Galuzzi, Elena Moscu Panainte, Yana Yankova,...
CODES
2006
IEEE
11 years 3 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
CODES
2006
IEEE
11 years 3 months ago
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel suppo...
Hayden Kwok-Hay So, Artem Tkachenko, Robert W. Bro...
CODES
2006
IEEE
11 years 3 months ago
Automatic phase detection for stochastic on-chip traffic generation
During System on Chip (SoC) design, Network on Chip (NoC) prototyping is used for adapting NoC parameters to the application running on the chip. This prototyping is currently don...
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset
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