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CODES
2008
IEEE
10 years 5 months ago
A performance-oriented hardware/software partitioning for datapath applications
This article proposes a hardware/software partitioning method targeted to performance-constrained systems for datapath applications. Exploiting a platform based design, a Timed Pe...
Laura Frigerio, Fabio Salice
CODES
2008
IEEE
10 years 5 months ago
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
The performance of system-on-chip is determined not only by the performance of its functional units, but also by how efficiently they cooperate with one another. It is the on-chip...
Huaxi Gu, Jiang Xu, Zheng Wang
CODES
2008
IEEE
10 years 5 months ago
Software optimization for MPSoC: a mpeg-2 decoder case study
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, trad...
Eric Cheung, Harry Hsieh, Felice Balarin
CODES
2008
IEEE
10 years 5 months ago
A time-predictable system initialization design for huge-capacity flash-memory storage systems
The capacity of flash-memory storage systems grows at a speed similar to many other storage systems. In order to properly manage the product cost, vendors face serious challenges ...
Chin-Hsien Wu
CODES
2008
IEEE
10 years 10 months ago
Asynchronous transient resilient links for NoC
This paper proposes a new link for asynchronous NoC communications that is resilient to transient faults on the wires of the link without impact on the data transfer capability. R...
Simon Ogg, Bashir M. Al-Hashimi, Alexandre Yakovle...
CODES
2008
IEEE
10 years 10 months ago
Reliable performance analysis of a multicore multithreaded system-on-chip
Simon Schliecker, Mircea Negrean, Gabriela Nicoles...
CODES
2008
IEEE
10 years 10 months ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra
CODES
2008
IEEE
10 years 10 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid
CODES
2008
IEEE
10 years 10 months ago
Extending open core protocol to support system-level cache coherence
Open Core Protocol (OCP) is a standard on-chip core interface specification. The current release is flexible and configurable to support the communication needs of a wide range...
Konstantinos Aisopos, Chien-Chun Chou, Li-Shiuan P...
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