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TCAD
1998
126views more  TCAD 1998»
13 years 4 months ago
Iterative remapping for logic circuits
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
Luca Benini, Patrick Vuillod, Giovanni De Micheli
IJIT
2004
13 years 5 months ago
Synthesis of Logic Circuits Using Fractional-Order Dynamic Fitness Functions
This paper analyses the performance of a genetic algorithm using a new concept, namely a fractional-order dynamic fitness function, for the synthesis of combinational logic circuit...
Cecília Reis, José António Te...
CSREAESA
2004
13 years 5 months ago
Switching Activity Minimization in Combinational Logic Design
: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal opt...
R. V. Menon, S. Chennupati, Naveen K. Samala, Damu...
EH
2003
IEEE
127views Hardware» more  EH 2003»
13 years 9 months ago
Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits
In this paper, we perform a comparative study of different heuristics used to design combinational logic circuits. The use of local search hybridized with a genetic algorithm and ...
Carlos A. Coello Coello, Enrique Alba, Gabriel Luq...
EUROGP
2004
Springer
135views Optimization» more  EUROGP 2004»
13 years 10 months ago
Reusing Code in Genetic Programming
Abstract. In this paper we propose an approach to Genetic Programming based on code reuse and we test it in the design of combinational logic circuits at the gate-level. The circui...
Edgar Galván López, Riccardo Poli, C...
GECCO
2005
Springer
128views Optimization» more  GECCO 2005»
13 years 10 months ago
Fractional dynamic fitness functions for GA-based circuit design
This paper proposes and analyses the performance of a Genetic Algorithm (GA) using two new concepts, namely a static fitness function including a discontinuity measure and a fract...
Cecília Reis, José António Te...
AHS
2006
IEEE
138views Hardware» more  AHS 2006»
13 years 10 months ago
Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures
Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has sh...
Emanuele Stomeo, Tatiana Kalganova, Cyrille Lamber...