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HPCA
2011
IEEE
8 years 6 months ago
CloudCache: Expanding and shrinking private caches
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilizatio...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
HPCA
2011
IEEE
8 years 6 months ago
Exploiting criticality to reduce bottlenecks in distributed uniprocessors
Composable multicore systems merge multiple independent cores for running sequential single-threaded workloads. The performance scalability of these systems, however, is limited d...
Behnam Robatmili, Madhu Saravana Sibi Govindan, Do...
MICRO
2010
IEEE
143views Hardware» more  MICRO 2010»
8 years 9 months ago
SD3: A Scalable Approach to Dynamic Data-Dependence Profiling
Abstract--As multicore processors are deployed in mainstream computing, the need for software tools to help parallelize programs is increasing dramatically. Data-dependence profili...
Minjang Kim, Hyesoon Kim, Chi-Keung Luk
DATE
2010
IEEE
108views Hardware» more  DATE 2010»
9 years 3 hour ago
Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors
Topology virtualization techniques are proposed for NoCbased many-core processors with core-level redundancy to isolate hardware changes caused by on-chip defective cores. Prior w...
Lei Zhang 0008, Yue Yu, Jianbo Dong, Yinhe Han, Sh...
AINA
2009
IEEE
9 years 13 days ago
Evaluating the Performance of Network Protocol Processing on Multi-core Systems
Improvements at the physical network layer have enabled technologies such as 10 Gigabit Ethernet. Single core end-systems are unable to fully utilise these networks, due to limite...
Matthew Faulkner, Andrew Brampton, Stephen Pink
IPPS
2010
IEEE
9 years 16 days ago
Decentralized resource management for multi-core desktop grids
The majority of CPUs now sold contain multiple computing cores. However, current desktop grid computing systems either ignore the multiplicity of cores, or treat them as distinct,...
Jaehwan Lee, Peter J. Keleher, Alan Sussman
VLSISP
2008
103views more  VLSISP 2008»
9 years 1 months ago
Power Signature Watermarking of IP Cores for FPGAs
In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This ...
Daniel Ziener, Jürgen Teich
INTEGRATION
1998
96views more  INTEGRATION 1998»
9 years 2 months ago
BIST for systems-on-a-chip
An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-provide...
Hans-Joachim Wunderlich
TODAES
2008
158views more  TODAES 2008»
9 years 2 months ago
Designing secure systems on reconfigurable hardware
The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integ...
Ted Huffmire, Brett Brotherton, Nick Callegari, Jo...
MICRO
2008
IEEE
79views Hardware» more  MICRO 2008»
9 years 2 months ago
Strategies for mapping dataflow blocks to distributed hardware
Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of depen...
Behnam Robatmili, Katherine E. Coons, Doug Burger,...
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