ERSA
2006
13 years 5 months ago
2006
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
IWOMP
2010
Springer
13 years 6 months ago
2010
Springer
With the approaching of the many-core era, it becomes more and more difficult for a single OpenMP application to efficiently utilize all the available processor cores. On the other...
HIPEAC
2009
Springer
13 years 7 months ago
2009
Springer
Shrinking process technologies and growing chip sizes have profound effects on process variation. This leads to Chip Multiprocessors (CMPs) where not all cores operate at maximum f...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP ...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
CASES
2006
ACM
13 years 8 months ago
2006
ACM
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...
ICN
2001
Springer
13 years 8 months ago
2001
Springer
Abstract. Core-based multicast trees use less router state, but have significant drawbacks when compared to shortest-path trees, namely higher delay and poor fault tolerance. We e...
CF
2010
ACM
13 years 9 months ago
2010
ACM
As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to des...
ICPP
2003
IEEE
13 years 9 months ago
2003
IEEE
In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-thre...
EH
2003
IEEE
13 years 9 months ago
2003
IEEE
The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectua...