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EUC
2005
Springer
13 years 10 months ago
An Integrated Scheme for Address Assignment and Service Location in Pervasive Environments
We propose an efficient scheme called CoReS (Configuration and Registration Scheme) that integrates address assignment and service location for ad hoc networks prevalent in pervasi...
Mijeom Kim, Mohan Kumar, Behrooz Shirazi
ISCA
2005
IEEE
81views Hardware» more  ISCA 2005»
13 years 10 months ago
The Impact of Performance Asymmetry in Emerging Multicore Architectures
Performance asymmetry in multicore architectures arises when individual cores have different performance. Building such multicore processors is desirable because many simple cores...
Saisanthosh Balakrishnan, Ravi Rajwar, Michael Upt...
IPPS
2005
IEEE
13 years 10 months ago
A Lightweight Scheme for Auto-configuration in Mobile Ad Hoc Networks
An efficient addressing scheme is necessary for auto-configuration and seamless communication in pervasive computing environments. In this paper, we propose an efficient and simple...
Mijeom Kim, Mohan Kumar, Behrooz Shirazi
CASES
2006
ACM
13 years 10 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
13 years 10 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
13 years 10 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
13 years 11 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
13 years 11 months ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks
DELTA
2008
IEEE
13 years 11 months ago
Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications
The advances of CMOS technology towards 45 nm, the high costs of ASIC design, power limitations and fast changing application requirements have stimulated the usage of highly reco...
Hans G. Kerkhoff, Jarkko J. M. Huijts
MICRO
2009
IEEE
113views Hardware» more  MICRO 2009»
13 years 11 months ago
The BubbleWrap many-core: popping cores for sequential acceleration
Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly i...
Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas