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ANCS
2009
ACM
13 years 2 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
TCS
2002
13 years 3 months ago
Threshold counters with increments and decrements
A threshold counter is a shared data structure that assumes integer values. It provides two operations:Increment changesthe current counter value from v to v
Costas Busch, Neophytos Demetriou, Maurice Herlihy...
CORR
2007
Springer
135views Education» more  CORR 2007»
13 years 4 months ago
Detailed Network Measurements Using Sparse Graph Counters: The Theory
— Measuring network flow sizes is important for tasks like accounting/billing, network forensics and security. Per-flow accounting is considered hard because it requires that m...
Yi Lu, Andrea Montanari, Balaji Prabhakar
COMCOM
2000
77views more  COMCOM 2000»
13 years 4 months ago
A location-based mobility tracking scheme for PCS networks
This paper introduces a location-based locating strategy for Personal Communication Services (PCS) systems. In the proposed scheme, location updates are based on the value of a mo...
Zuji Mao, Christos Douligeris
SIGMETRICS
2008
ACM
13 years 4 months ago
DRAM is plenty fast for wirespeed statistics counting
Per-flow network measurement at Internet backbone links requires the efficient maintanence of large arrays of statistics counters at very high speeds (e.g. 40 Gb/s). The prevailin...
Bill Lin, Jun (Jim) Xu
SIGMETRICS
2008
ACM
181views Hardware» more  SIGMETRICS 2008»
13 years 4 months ago
Counter braids: a novel counter architecture for per-flow measurement
Fine-grained network measurement requires routers and switches to update large arrays of counters at very high link speed (e.g. 40 Gbps). A naive algorithm needs an infeasible amo...
Yi Lu, Andrea Montanari, Balaji Prabhakar, Sarang ...
CAL
2006
13 years 4 months ago
Probabilistic counter updates for predictor hysteresis and bias
Hardware predictor designers have incorporated hysteresis and/or bias to achieve desired behavior by increasing the number of bits per counter. Some resulting proposed predictor de...
Nicholas Riley, Craig B. Zilles
CONCUR
2008
Springer
13 years 6 months ago
R-Automata
R-automata are finite state machines extended with counters which can be incremented or reset to zero along the transitions. The universality question asks whether there is a cons...
Parosh Aziz Abdulla, Pavel Krcál, Wang Yi
ISCA
2006
IEEE
123views Hardware» more  ISCA 2006»
13 years 10 months ago
Improving Cost, Performance, and Security of Memory Encryption and Authentication
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encrypt...
Chenyu Yan, Daniel Englender, Milos Prvulovic, Bri...