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CSREAESA
2009
9 years 3 months ago
Application of Embedded Systems in Low Earth Orbit for Measurement of Ionospheric Anomalies
: Space is a hazardous environment for both man and machine and to explore such a terrain a rugged, yet easily implementable, platform is needed. Low-cost, low-power embedded syste...
George J. Starr, J. M. Wersinger, Richard Chapman,...
CSREAESA
2009
9 years 3 months ago
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...
CSREAESA
2009
9 years 3 months ago
Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
Bradley F. Dutton, Charles E. Stroud
CSREAESA
2003
9 years 3 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
CSREAESA
2003
9 years 3 months ago
Low-Power Dynamic Scheduling in Heterogeneous Systems
: This paper develops a matching and scheduling algorithm that accounts for both the execution time and the power consumption of the application. The power consumption of different...
Saumya Uppaluri, Baback A. Izadi, Damu Radhakrishn...
CSREAESA
2003
9 years 3 months ago
Verification Patterns for Rapid Embedded System Verification
Wei-Tek Tsai, Feng Zhu, Lian Yu, Raymond A. Paul, ...
CSREAESA
2003
9 years 3 months ago
Worst Case Execution Time Analysis for Petri Net Models of Embedded Systems
We present an approach for Worst-Case Execution Time (WCET) Analysis of embedded system software, that is generated from Petri net specifications. The presented approach is part ...
Friedhelm Stappert, Carsten Rust
CSREAESA
2003
9 years 3 months ago
Design of Digital Circuits on the Basis of Hardware Templates
The paper presents a technique for the design of digital circuits based on reusable hardware templates (HT). Any HT is being constructed in such a way that it might be employed for...
Valery Sklyarov, Iouliia Skliarova
CSREAESA
2003
9 years 3 months ago
Impact of Code Compression on the Power Consumption in Embedded Systems
Future embedded systems (ES) will offer higher computation capacity than existing embedded systems. New applications of these ES require more and more memory resources and more an...
N. Kadri, S. Niar, A. R. Baba-Ali
CSREAESA
2003
9 years 3 months ago
Common Mistakes in Adiabatic Logic Design and How to Avoid Them
Most so-called “adiabatic” digital logic circuit families reported in the low-power design literature are actually not truly adiabatic, in that they do not satisfy the general...
Michael P. Frank
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