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    DAC
    1994
    ACM
    88views Computer Architecture» more  DAC 1994»
    Error Diagnosis for Transistor-Level Verification
    13 years 8 months ago
    Error Diagnosis for Transistor-Level Verification
    Download  www.cadence.com
    This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagat...
    Andreas Kuehlmann, David Ihsin Cheng, Arvind Srini...
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    DAC
    1994
    ACM
    101views Computer Architecture» more  DAC 1994»
    A Fully Implicit Algorithm for Exact State Minimization
    13 years 8 months ago
    A Fully Implicit Algorithm for Exact State Minimization
    Download  www.cs.york.ac.uk
    State minimization of incompletely specifiedmachinesis an important step of FSM synthesis. An exact algorithm consists of generation of prime compatibles and solution of a binate ...
    Timothy Kam, Tiziano Villa, Robert K. Brayton, Alb...
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    DAC
    1994
    ACM
    94views Computer Architecture» more  DAC 1994»
    Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model
    13 years 8 months ago
    Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model
    Download  www.cs.york.ac.uk
    Andrew B. Kahng, Sudhakar Muddu
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    DAC
    1994
    ACM
    142views Computer Architecture» more  DAC 1994»
    Statistical Delay Modeling in Logic Design and Synthesis
    13 years 8 months ago
    Statistical Delay Modeling in Logic Design and Synthesis
    Download  www.cs.york.ac.uk
    Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
    Horng-Fei Jyu, Sharad Malik
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    DAC
    1994
    ACM
    115views Computer Architecture» more  DAC 1994»
    A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules
    13 years 8 months ago
    A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules
    Download  www.cecs.uci.edu
    Current asynchronous tools are focussed mainly on the design of a single interface module. In many applications, one must design interacting interface modules that potentially comm...
    Gjalt G. de Jong, Bill Lin
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    DAC
    1994
    ACM
    106views Computer Architecture» more  DAC 1994»
    Technology Mapping Using Fuzzy Logic
    13 years 8 months ago
    Technology Mapping Using Fuzzy Logic
    Download  www.cs.york.ac.uk
    - This paper presents a placement-driven technology mapping procedure based on fuzzy delay curves. The fuzziness has been introduced to deal with the inherent vagueness in wiring l...
    Sasan Iman, Massoud Pedram, Kamal Chaudhary
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    DAC
    1994
    ACM
    89views Computer Architecture» more  DAC 1994»
    Synthesis of Instruction Sets for Pipelined Microprocessors
    13 years 8 months ago
    Synthesis of Instruction Sets for Pipelined Microprocessors
    Download  cadal.cse.nsysu.edu.tw
    We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
    Ing-Jer Huang, Alvin M. Despain
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    DAC
    1994
    ACM
    93views Computer Architecture» more  DAC 1994»
    An Efficient Path Delay Fault Coverage Estimator
    13 years 8 months ago
    An Efficient Path Delay Fault Coverage Estimator
    Download  www.cs.york.ac.uk
    Keerthi Heragu, Michael L. Bushnell, Vishwani D. A...
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    DAC
    1994
    ACM
    118views Computer Architecture» more  DAC 1994»
    A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI's
    13 years 8 months ago
    A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI's
    Download  www.cs.york.ac.uk
    Ikuo Harada, Hitoshi Kitazawa
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    DAC
    1994
    ACM
    100views Computer Architecture» more  DAC 1994»
    Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-Based Designs
    13 years 8 months ago
    Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-Based Designs
    Download  www.cs.york.ac.uk
    Anurag P. Gupta, Daniel P. Siewiorek
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