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DAC
1994
ACM
9 years 7 months ago
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
Wen-Chang Fang, Sandeep K. Gupta
DAC
1994
ACM
9 years 7 months ago
Acyclic Multi-Way Partitioning of Boolean Networks
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
Jason Cong, Zheng Li, Rajive Bagrodia
DAC
1994
ACM
9 years 7 months ago
Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems
Existing software scheduling techniques limit the functions that can be implemented in software to those with a restricted class of timing constraints, in particular those with a c...
Pai H. Chou, Gaetano Borriello
DAC
1994
ACM
9 years 7 months ago
Simultaneous Placement and Module Optimization of Analog IC's
New placement techniques are presented which substantially improve the process of automatic layout generation of analog IC's. Extremely tight specifications can be enforced o...
Edoardo Charbon, Enrico Malavasi, Davide Pandini, ...
DAC
1994
ACM
9 years 7 months ago
Layout Driven Logic Synthesis for FPGAs
Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, ...
DAC
1994
ACM
9 years 7 months ago
MIST - A Design Aid for Programmable Pipelined Processors
-- In this paper, a tool to aid pipelined processor instruction set implementation is described. The purpose of the tool is to choose from among design alternatives a design that m...
Albert E. Casavant
DAC
1994
ACM
9 years 7 months ago
Rectilinear Steiner Trees with Minimum Elmore Delay
We provide a new theoretical framework for constructing Steiner routing trees with minimum Elmore delay. Earlier work [3, 13] has established Elmore delay as a high delity estima...
Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCo...
DAC
1994
ACM
9 years 7 months ago
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications
This paper presents a new method,based on Markov chain analysis, to evaluate the performance of schedules of behavioral specifications. The proposed performance measure is the expe...
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
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