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    DAC
    1996
    ACM
    113views Computer Architecture» more  DAC 1996»
    Efficient Software Performance Estimation Methods for Hardware/Software Codesign
    13 years 8 months ago
    Efficient Software Performance Estimation Methods for Hardware/Software Codesign
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    Kei Suzuki, Alberto L. Sangiovanni-Vincentelli
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    DAC
    1996
    ACM
    121views Computer Architecture» more  DAC 1996»
    A Description Language for Design Process Management
    13 years 8 months ago
    A Description Language for Design Process Management
    Download  www.itee.uq.edu.au
    A language for defining design discipline characteristics is proesign discipline characteristics such as abstraction levels, design object classifications and decompositions, desi...
    Peter R. Sutton, Stephen W. Director
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    DAC
    1996
    ACM
    97views Computer Architecture» more  DAC 1996»
    Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance
    13 years 8 months ago
    Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance
    Download  www.soe.ucsc.edu
    Measured Equation of Invariance(MEI) is a new concept in computational electromagnetics. It has been demonstrated that the MEI technique can be used to terminate the meshes very c...
    Weikai Sun, Wayne Wei-Ming Dai, Wei Hong II
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    DAC
    1996
    ACM
    87views Computer Architecture» more  DAC 1996»
    Implementation of an Efficient Parallel BDD Package
    13 years 8 months ago
    Implementation of an Efficient Parallel BDD Package
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    Tony Stornetta, Forrest Brewer
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    DAC
    1996
    ACM
    99views Computer Architecture» more  DAC 1996»
    Software Development in a Hardware Simulation Environment
    13 years 8 months ago
    Software Development in a Hardware Simulation Environment
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    Concurrent verification of hardware and software as part of the development process can shorten the time to market of complex systems. The objectives of the Virtual CPU approach i...
    Benny Schnaider, Einat Yogev
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    DAC
    1996
    ACM
    148views Computer Architecture» more  DAC 1996»
    RTL Emulation: The Next Leap in System Verification
    13 years 8 months ago
    RTL Emulation: The Next Leap in System Verification
    Download  www.cs.york.ac.uk
    ion. Production use of text-based methodology has enabled designers to capture designs of hundreds of thousands of gates using graphic ESDA tools. Source: Data Quest (Verilog/VHDL ...
    Sanjay Sawant, Paul Giordano
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    DAC
    1996
    ACM
    81views Computer Architecture» more  DAC 1996»
    Post-Layout Optimization for Deep Submicron Design
    13 years 8 months ago
    Post-Layout Optimization for Deep Submicron Design
    Download  www.cs.york.ac.uk
    To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buers based on back-annotated detailed routing information. D...
    Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emu...
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    DAC
    1996
    ACM
    102views Computer Architecture» more  DAC 1996»
    Tutorial: Design of a Logic Synthesis System
    13 years 8 months ago
    Tutorial: Design of a Logic Synthesis System
    Download  www.eng.ucy.ac.cy
    Logic synthesis systems are complex systems and algorithmic research in synthesis has become highly specialized. This creates a gap where it is often not clear how an advance in a...
    Richard L. Rudell
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    DAC
    1996
    ACM
    156views Computer Architecture» more  DAC 1996»
    Glitch Analysis and Reduction in Register Transfer Level
    13 years 8 months ago
    Glitch Analysis and Reduction in Register Transfer Level
    Download  vswww.kaist.ac.kr
    : We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
    Anand Raghunathan, Sujit Dey, Niraj K. Jha
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    DAC
    1996
    ACM
    94views Computer Architecture» more  DAC 1996»
    Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor
    13 years 8 months ago
    Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor
    Download  www.cecs.uci.edu
    Superscalar processor developers are creatively leveraging best-in-class design verification tools to meet narrow market windows. Accelerated simulation is especially useful owing...
    Val Popescu, Bill McNamara
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